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PRELIMINARY
Am29LV008T/Am29LV008B
8 Megabit (1,048,576 x 8-Bit) CMOS 3.0 Volt-only, Sectored Flash Memory 3.0 V-only Flash
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- Extended voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications -- Standard voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s High performance -- Extended voltage range: access times as fast as 100 ns -- Standard voltage range: access times as fast as 90 ns s Ultra low power consumption -- Automatic Sleep Mode: 200 nA typical -- Standby mode: 200 nA typical -- Read mode: 2 mA/MHz typical -- Program/erase mode: 20 mA typical s Flexible sector architecture -- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors -- Supports control code and data storage on a single device -- Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Temporary Sector Unprotect feature allows code changes in previously locked sectors s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithms automatically preprogram and erase the entire chip or any combination of designated sectors -- Embedded Program algorithms automatically write and verify bytes or words at specified addresses s Minimum 100,000 write cycle guarantee per sector s Package option -- 40-pin TSOP s Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection s Data Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Ready/Busy pin -- Provides a hardware method of detecting program or erase cycle completion s Erase suspend/resume feature -- Provides the ability to suspend the erase operation in any sector, read data from or program data to any other sector, then return to the original sector and complete the initial erase operation s Hardware reset pin (RESET) -- Hardware method to reset the device to the read mode
GENERAL DESCRIPTION
The Am29LV008 is an 8 Mbit, 3.0 Volt-only Flash memory organized as 512 Kbytes of 8 bits each. For flexible erase and program capability, the 512 Kbits of data is divided into 19 sectors of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbytes. The data appears on DQ0-DQ7. The Am29LV008 is offered in a 40-pin TSOP package. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. The device can also be reprogrammed in standard EPROM programmers. The Am29LV008 provides two levels of performance. The first level offers access times as fast as 100 ns with a VCC range as low as 2.7 volts, which is optimal for battery powered applications. The second level offers a
Publication# 20511 Rev: C Amendment/+1 Issue Date: May 1997
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
PRELIMINARY 90 ns access time, optimizing performance in systems where the power supply is in the regulated range of 3.0 to 3.6 volts. To eliminate bus contention, the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The Am29LV008 is entirely command set-compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Am29LV008 is programmed by executing the program command sequence. This invokes the Embedded Program Algorithm, which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The device is erased by executing the erase command sequence. This invokes the Embedded Erase Algorithm, which is an internal algorithm that automatically preprograms the array, if it is not already programmed, before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. This device also features a sector erase architecture. This allows for sectors of memory to be erased and reprogrammed without affecting the data contents of other sectors. A sector is typically erased and verified within 1.0 second. The Am29LV008 is fully erased when shipped from the factory. The Am29LV008 device also features hardware sector protection, implemented via external programming equipment, which disables both program and erase operations in any combination of the memory sectors. The Erase Suspend feature enables the user to pause the erase operation, for any period of time, to read data from or program data to a sector that was not being erased. Thus, true background erase can be achieved. The device features 3.0 volt, single-power-supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by the RY/BY pin. Data Polling of DQ7, or by the Toggle Bit (DQ6). Once the end of a program or erase cycle has been completed, the device automatically resets to the read mode. The Am29LV008 also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program or Erase Algorithm will be terminated. The internal state machine is then be reset into the read mode. Resetting the device will enable the system's microprocessor to read the boot-up firmware from the Flash memory. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The Am29LV008 memory electrically erases all bits within a sector simultaneously via FowlerNordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
2
Am29LV008T/Am29LV008B
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Ordering Part Number: VCC = 3.0-3.6 V VCC = 2.7-3.6 V Max access time (ns) CE access time (ns) OE access time (ns) 90 90 40 -90R -100 100 100 40 -120 120 120 50 -150 150 150 55 Am29LV008T/Am29LV008B
3.0 V-only Flash
BLOCK DIAGRAM
RY/BY VCC VSS RESET Sector Switches DQ0-DQ7
Erase Voltage Generator State Control Command Register
Input/Output Buffers
WE BYTE
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE OE
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A19
20511C-1
Am29LV008T/Am29LV008B
3
PRELIMINARY
CONNECTION DIAGRAMS
A16 A15 A14 A13 A12 A11 A9 A8 WE RESET NC RY/BY A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Standard 40-Pin TSOP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 VSS NC A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE VSS CE A0
A17 VSS NC A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 CE VSS CE A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Reverse 40-Pin TSOP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A16 A15 A14 A13 A12 A11 A9 A8 WE RESET NC RY/BY A18 A7 A6 A5 A4 A3 A2 A1
20511C-2
4
Am29LV008T/Am29LV008B
PRELIMINARY
PIN CONFIGURATION
A0-A19 DQ0-DQ7 CE OE WE RESET RY/BY VCC = 20 addresses = 8 data inputs/outputs = Chip enable = Output enable = Write enable = Hardware reset pin, active low = Ready/Busy output = Standard voltage range (3.0 V to 3.6 V) for -90R Extended voltage range (2.7 to 3.6 V) for -100, -120, -150 VSS NC = Device ground = Pin not connected internally
LOGIC SYMBOL
20 A0-A19 DQ0-DQ7
3.0 V-only Flash
8
CE (E) OE (G) WE (W) RESET RY/BY
20511C-3
Am29LV008T/Am29LV008B
5
PRELIMINARY
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29LV008
T
-90R
E
C
OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) E = Extended (-55C to +125C) PACKAGE TYPE E = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040) F = 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040) SPEED OPTION -xxx = 2.7 to 3.6 V VCC -xxR = 3.0 to 3.6 V VCC See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector
DEVICE NUMBER/DESCRIPTION Am29LV008 8 Megabit (1 M x 8-Bit) CMOS Flash Memory 3.0 Volt-only Program and Erase
Valid Combinations Am29LV008T-90R, Am29LV008B-90R VCC = 3.0-3.6 V AM29LV008T-100, Am29LV008B-100 Am29LV008T-120, Am29LV008B-120 Am29LV008T-150, Am29LV008B-150 EC, EI, EE, EEB, FC, FI, FE, FEB EC, EI, FC, FI
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
6
Am29LV008T/Am29LV008B
PRELIMINARY Table 1.
Operation Autoselect, Manufacturer Code (Note 1) Autoselect, Device Code (Note 1) Read Standby Output Disable Write Enable Sector Protect (Note 3) Verify Sector Protect (Note 4) Temporary Sector Unprotect Reset CE L L L H L L L L X X
Am29LV008 User Bus Operations
OE L L L X H H VID L X X WE H H H X H L Pulse/H H X X A0 L H A0 X X A0 L L X X A1 L L A1 X X A1 H H X X A6 L L A6 X X A6 L L X X A9 VID VID A9 X X A9 VID VID X X DQ0-DQ7 Code Code RD HIGH Z HIGH Z PD (Note 2) Code Code X HIGH Z RESET
3.0 V-only Flash
H H H H H H H H VID L
Legend: L = VIL, H = VIH, VID = 12.0 V 5%, X = Don't care. See "DC Characteristics" on page 26 for voltage levels. PD = program data, RD = read data. Refer to Table 3 on page 10 for more information. Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5 on page 13. 2. Refer to Table 5 for valid PD during a write operation. 3. Set VCC = 3.0 volts 10%. 4. Refer to "Sector Protection" on page 12.
Am29LV008T/Am29LV008B
7
PRELIMINARY
USER BUS OPERATIONS Read Mode
The Am29LV008 has three control functions which must be satisfied in order to obtain data at the outputs: s CE is the power control and should be used for device selection (CE = VIL) s OE is the output control and should be used to gate data to the output pins if the device is selected (OE = VIL) s WE remains at VIH Address access time (TACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (TCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time (TOE) is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable at least TACC - TOE time).
Deselecting CE (CE and RESET = VCC 0.3 V) puts the device into the ICC3 standby mode. If the device is deselected during an Embedded Algorithm operation, it continues to draw active power (ICC2) prior to entering the standby mode, until the operation is complete. When the device is again selected (CE = VIL), active operations occur in accordance with the AC timing specifications.
Automatic Sleep Mode
Advanced power management features such as the automatic sleep mode minimize Flash device energy c o n s u m p t i o n . T h i s i s ex t r e m e l y i m p o r t a n t i n battery-powered applications. The Am29LV008 automatically enables the low-power, automatic sleep mode when addresses remain stable for 200 ns. Automatic sleep mode is independent of the CE, WE, and OE control signals. Typical sleep mode current draw is 200 nA (for CMOS-compatible operation). Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system.
Standby Mode
The Am29LV008 is designed to accommodate low standby power consumption by applying the following voltages to the CE and RESET pins: ICC3 for CMOS compatible I/Os (current consumption <5 A max.) is enabled when a CMOS logic level `1' (VCC 0.3 V) is applied to the CE control pin with RESET = VCC 0.3 V. While in the ICC3 standby mode, the data I/O pins remain in the high impedance state independent of the voltage level applied to the OE input. See the DC Characteristics section for more details on Standby Modes.
Output Disable
If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state.
8
Am29LV008T/Am29LV008B
PRELIMINARY
Autoselect
The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. The intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The Autoselect command may also be used to check the status of write-protected sectors (see Table 2). This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (12.0 V 5%) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0, A1, and A6 see Table 2. The manufacturer and device codes may also be read via the command register, for instances when the
Am29LV008 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 5 on page 13.
3.0 V-only Flash
Byte 0 (A0 = VIL) represents the manufacturer's code and byte 1 (A0 = VIH) the device identifier code. For the Am29LV008 these two bytes are given in Table 2. All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing Autoselect, A1 must be VIL (see Table 2). The device code is 3EH (for top boot block) or 37H (for bottom boot block). In order to determine which sectors are write protected, A1 must be at VIH while running through the sector addresses; if the selected sector is protected, a logical `1' will be output on DQ0 (DQ0 = 1).
Table 2.
Type Manufacturer Code: AMD 29LV008 Device (Top Boot Block) 29LV008 Device (Bottom Boot Block) Sector Protection A13-A19 X X X Set Sector Addresses A6 L L L L
Autoselect/Sector Protection Codes
A1 L L L H A0 L H H L Code (HEX) 01H 3EH 37H 01H* DQ 7 0 0 0 0 DQ 6 0 0 0 0 DQ 5 0 1 1 0 DQ 4 0 1 1 0 DQ 3 0 1 0 0 DQ 2 0 1 1 0 DQ 1 0 1 1 0 DQ 0 1 0 1 1
X = Don't care. * Outputs 01H at protected sector addresses.
Am29LV008T/Am29LV008B
9
PRELIMINARY Table 3.
A19 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1
Sector Address Tables (Am29LV008T)
A15 X X X X X X X X X X X X X X X 0 1 1 1 A14 X X X X X X X X X X X X X X X X 0 0 1 A13 X X X X X X X X X X X X X X X X 0 1 X Sector Size 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 32 Kbytes 8 Kbytes 8 Kbytes 16 Kbytes Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh 80000h-8FFFFh 90000h-9FFFFh A0000h-AFFFFh B0000h-BFFFFh C0000h-CFFFFh D0000h-DFFFFh E0000h-EFFFFh F0000h-F7FFFh F8000h-F9FFFh FA000h-FBFFFh FC000h-FFFFFh
10
Am29LV008T/Am29LV008B
PRELIMINARY Table 4.
A19 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A17 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Sector Address Tables (Am29LV008B)
A15 0 0 0 1 X X X X X X X X X X X X X X X A14 0 1 1 X X X X X X X X X X X X X X X X A13 X 0 1 X X X X X X X X X X X X X X X X Sector Size 16 Kbytes 8 Kbytes 8 Kbytes 32 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Address Range 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh 80000h-8FFFFh 90000h-9FFFFh A0000h-AFFFFh B0000h-BFFFFh C0000h-CFFFFh D0000h-DFFFFh E0000h-EFFFFh F0000h-FFFFFh
3.0 V-only Flash
Am29LV008T/Am29LV008B
11
PRELIMINARY
Write
Device erasure and programming are accomplished via the command register. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of CE or WE, whichever occurs later, while data is latched on the rising edge of the CE or WE pulse, whichever occurs first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/ Programming Waveforms for specific timing parameters.
ing them in the improper sequence will reset the device to the read mode. Table 5 on page 13 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress.
Read/Reset Command
The device will automatically power up in the read/ reset state. In this case, a command sequence is not required to read data. Standard microprocessor cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Characteristics section for the specific timing parameters. The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered.
Sector Protection
Sectors of the Am29LV008 may be hardware protected at the user's factory with external programming equipment. The protection circuitry will disable both program and erase functions for the protected sectors, making the protected sectors read-only. Requests to program or erase a protected sector will be ignored by the device. If the user attempts to write to a protected sector, DATA Polling will be activated for about 1 s; the device will then return to read mode, with data from the protected sector unchanged. If the user attempts to erase a protected sector, Toggle Bit will be activated for about 50 s; the device will then return to read mode, without having erased the protected sector. It is possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order address A18-A12 represents the sector address, will produce a logical `1' at DQ0 for a protected sector.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. The Am29LV008 contains an autoselect command operation that provides device information and sector protection status to the system. The operation is initiated by writing the autoselect command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacturer code of 01H. A read cycle from address XX01H returns the device code 3EH (for top boot device) or 37H (for bottom boot device); see Table 2 on page 9. All manufacturer and device codes will exhibit odd parity with the MSB of the lower byte (DQ7) defined as the parity bit. Scanning the sector addresses (A13, A14, A15, A16, A17, A18, and A19) while (A6, A1, A0) = (0, 1, 0) will produce a logical `1' code at device output DQ0 for a write protected sector (See Table 2). To terminate the Autoselect operation, it is necessary to write the read/reset command sequence into the register.
Temporary Sector Unprotect
The sectors of the Am29LV008 may be temporarily unprotected by raising the RESET pin to 12.0 volts (VID). During this mode, formerly protected sectors can be programmed or erased with standard command sequences by selecting the appropriate byte or sector addresses. Once the RESET pin goes to V IH , all the previously protected sectors will be protected again.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writ-
12
Am29LV008T/Am29LV008B
PRELIMINARY Table 5.
Command Sequence Read/Reset (Note 2) Reset/Read Autoselect Manufacturer ID Autoselect Device ID (Top Boot Block) Autoselect Device ID (Bottom Boot Block) Autoselect Sector Protect Verify (Note 3) Byte Program Chip Erase Sector Erase Erase Suspend (Note 4) Erase Resume (Note 5) Bus First Bus Write Write Cycle Cycles Req'd Addr Data 1 3 XXX 555 F0 AA
Am29LV008 Command Definitions
Second Bus Read/Write Cycle Addr RA 2AA Data RD 55 555 90 X00 01 Third Bus Write Cycle Addr Data Fourth Bus Read/Write Cycle Addr Data Fifth Bus Write Cycle Addr Data Sixth Bus Write Cycle Addr Data
3.0 V-only Flash
3
555
AA
2AA
55
555
90
X01
3E
3
555
AA
2AA
55
555
90
X01
37 00 01 PD AA AA 2AA 2AA 55 55 555 SA 10 30
3 4 6 6 1 1
555 555 555 555 XXX XXX
AA AA AA AA B0 30
2AA 2AA 2AA 2AA
55 55 55 55
555 555 555 555
90 A0 80 80
SA X02 PA 555 555
Legend: RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse. SA = Address of the sector to be erased or verified. Address bits A19-A13 uniquely select any sector. Notes: 1. All values are in hexadecimal. 2. See Table 1 for description of bus operations. 3. The data is 00h for an unprotected sector and 01h for a protected sector. The complete bus address is composed of the sector address on A19-A13 and 02h on A7-A0. 4. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 5. The Erase Resume command is valid only during the Erase Suspend mode. 6. Unless otherwise noted, address bits A19-A11 = X = don't care.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. There are two "unlock" write cycles. These are followed by the program command and address/data write cycles. Addresses are latched on the falling edge of CE or WE, whichever occurs later, while the data is latched on the rising edge of CE or WE, whichever occurs first. The rising edge of CE or WE, whichever occurs first, initiates programming using the Em-
bedded Program Algorithm. Upon executing the write command, the system is not required to provide further controls or timing. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The status of the Embedded Program Algorithm operation can be determined three ways: s DATA Polling of DQ7
Am29LV008T/Am29LV008B
13
PRELIMINARY s Checking the status of the toggle bit DQ6 s Checking the status of the RY/BY pin Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during a programming operation, the data at that location will be corrupted. Programming is allowed in any sequence and across sector boundaries. Beware that a data `0' cannot be programmed back to a `1'. Attempting to do so will cause the device to exceed programming time limits (DQ5 = 1) or result in an apparent success according to the data polling algorithm. However, reading the device after executing the Read/ Reset operation will show that the data is still `0'. Only erase operations can convert `0's to `1's. Figure 4 illustrates the Embedded Program Algorithm, using typical command strings and bus operations. then following it by additional writes of the Sector Erase command to addresses of other sectors to be erased. The time between Sector Erase command writes must be less than 80 s, otherwise that command will not be accepted. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 80 s from the rising edge of the last WE (or CE) will initiate the execution of the Sector Erase command(s). If another falling edge of the WE (or CE) occurs within the 80 s time-out window, the timer is reset. During the 80 s window, any command other than Sector Erase or Erase Suspend written to the device will reset the device back to Read mode. Once the 80 s window has timed out, only the Erase suspend command is recognized. Note that although the Reset command is not recognized in the Erase Suspend mode, the device is available for read or program operations in sectors that are not erase suspended. The Erase Suspended and Erase Resume commands may be written as often as required during a sector erase operation. Hence, once erase has begun, it must ultimately complete unless Hardware Reset is initiated. Loading the sector erase registers may be done in any sequence and with any number of sectors (0 to 18). Sector erase does not require the user to program the device prior to erase. The device automatically preprograms all memory locations, within sectors to be erased, prior to electrical erase. When erasing a sector or sectors, the remaining unselected sectors or the write protected sectors are unaffected. The system is not required to provide any controls or timings during sector erase operations. The Erase Suspend and Erase Resume commands may be written as often as required during a sector erase operation. Automatic sector erase operations begin on the rising edge of the WE (or CE) pulse of the last sector erase command issued, and once the 80 s time-out window has expired. The status of the sector erase operation can be determined three ways: s DATA Polling of DQ7 s Checking the status of the toggle bit DQ6 s Checking the status of the RY/BY pin Further status of device activity during the sector erase operation can be determined using toggle bits DQ2 and DQ3. Figure 5 illustrates the Embedded Erase Algorithm, using a typical command sequence and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles, followed by writing the erase "set up" command. Two more "unlock" write cycles are followed by the chip erase command. Chip erase does not require the user to preprogram the device to all `0's prior to erase. Upon executing the Embedded Erase Algorithm command sequence, the device automatically programs and verifies the entire memory to an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Embedded Erase Algorithm erase begins on the rising edge of the last WE or CE (whichever occurs first) pulse in the command sequence. The status of the Embedded Erase Algorithm operation can be determined three ways: s DATA Polling of DQ7 s Checking the status of the toggle bit DQ6 s Checking the status of the RY/BY pin Figure 5 illustrates the Embedded Erase Algorithm, using a typical command sequence and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" writes. These are followed by writing the erase "set up" command. Two more "unlock" writes are followed by the Sector Erase command (30H). The sector address (any address location within the desired sector) is latched on the falling edge of WE or CE (whichever occurs last) while the command (30H) is latched on the rising edge of WE or CE (whichever occurs first). Multiple sectors can be specified for erase by writing the six bus cycle operation as described above and
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data
14
Am29LV008T/Am29LV008B
PRELIMINARY read or programs in a sector not being erased. This command is applicable only during the Sector Erase operation, which includes the time-out period for Sector Erase. The Erase Suspend command will be ignored if written during the execution of the Chip Erase operation or Embedded Program Algorithm (but will reset the chip if written improperly during the command sequences.) Writing the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Once in Erase Suspend, the device is available for read (note that in the Erase Suspend mode, the Reset/Read command is not required for read operations and is ignored) or program operations in sectors not being erased. Any other command written during the Erase Suspend mode will be ignored, except for the Erase Resume command. Writing the Erase Resume command resumes the sector erase operation. The addresses are "don't cares" when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during a Sector Erase operation, the chip will take between 0.1 s and 20 s to actually suspend the operation and go into erase suspended read mode (pseudo-read mode), at which time the user can read or program from a sector that is not erase suspended. Reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. Polling DQ2 on successive reads from a given sector provides the system the ability to determine if a sector is in Erase Suspend. After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Byte Program. This program mode is known as the erase suspend-program mode. Again, programming in this mode is the same as programming in the regular Byte Program mode, except that the data must be programmed to sectors that are not erase suspended. Successively reading from the erase suspended sector while the device is in the erase suspend-program mode will cause DQ2 to toggle. Completion of the erase suspend operation can be determined two ways: s Checking the status of the toggle bit DQ2 s Checking the status of the RY/BY pin To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. However, another Erase Suspend command can be written after the device has resumed sector erase operations. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be r e a d f r o m s e c t o r s t h a t h ave n o t b e e n erase-suspended. To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
3.0 V-only Flash
Write Operation Status
Address Sensitivity of Write Status Flags Detailed in Table 6 are all the status flags that can be used to check the status of the device for current mode operation. During Sector Erase, the part provides the status flags automatically to the I/O ports. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which sectors are erasing and which are not. Once Erase Suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. If the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits. Confirmation of status bits can be done by doing consecutive reads to toggle DQ2, which is active throughout the Embedded Erase mode, including Erase Suspend. In order to effectively use DATA Polling to determine if the device has entered into erase-suspended mode, it is necessary to apply a sector address from a sector being erased.
Am29LV008T/Am29LV008B
15
PRELIMINARY Table 6.
Status Programming Program/Erase in Auto-Erase Erase Sector Address Erase Suspend Mode Non-Erase Sector Address Program in Erase Suspend Programming Exceeded Time Limits Program/Erase in Auto-Erase Program in Erase Suspend
Hardware Sequence Flags
DQ7 DQ7 0 1 Data DQ7 (Note 2) DQ7 0 DQ7 DQ6 Toggle Toggle No Toggle Data Toggle Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 0 1 0 Data 0 0 1 0 DQ2 No Toggle (Note 1) Toggle (Note 1) Data (Note 2) 1 (Note 2) No Toggle (Note 3) No Toggle RY/BY 0 0 1 1 0 0 0 0
In Progress
Notes: 1. DQ2 can be toggled when the sector address applied is that of an erasing or erase suspended sector. Conversely, DQ2 cannot be toggled when the sector address applied is that of a non-erasing or non-erase suspended sector. DQ2 is therefore used to determine which sectors are erasing or erase suspended and which are not. 2. These status flags apply when outputs are read from the address of a non-erase-suspended sector. 3. If DQ5 is high (exceeded timing limits), successive reads from a problem sector will cause DQ2 to toggle.
DQ7: Data Polling The Am29LV008 features DATA Polling as a method to indicate to the host system that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the compliment of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. Note that just at the instant when DQ7 switches to true data, the other bits, DQ6-DQ0, may not yet be true data. However, they will all be true data on the next read from the device. Please note that Data Polling (DQ7) may give an inaccurate result when an attempt is made to write to a protected sector. During an Embedded Erase Algorithm, an attempt to read the device will produce a `0' at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read t h e d ev i c e w i l l p r o d u c e a ` 1 ' a t D Q 7 . For chip erase, the DATA Polling is valid (DQ7 = 1) after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the DATA Polling is valid after the last rising edge of the sector erase WE pulse. DATA Polling must be performed at sector addresses within any of the sectors being erased and not a sector that is within a protected sector. Otherwise, the status may not be valid. Just prior to the completion of Embedded Algorithm operations, DQ7 may change asynchronously while the output enable (OE) is asserted low. This means that the
device is driving status information on DQ7 at one instant of time and in the next instance of time, that byte has valid data. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has valid data, DQ0- DQ6 may still provide write operation status. The valid data on DQ0-DQ7 can be read on the next successive read attempt. The DATA Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, erase suspend-program mode, or sector erase time-out (see Table 6). If the user attempts to write to a protected sector, DATA Polling will be activated for about 1 s; the device will then return to read mode, with data from the protected sector unchanged. If the user attempts to erase a protected sector, Toggle Bit will be activated for about 50 s; the device will then return to read mode, without having erased the protected sector. See Figure 6 for the DATA Polling timing specifications and diagrams. DQ6: Toggle Bit The Am29LV008 also features a "Toggle Bit" as a method to indicate to the host system whether the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm, successive attempts to read data from the device will result in DQ6 toggling between one and zero. Once the
16
Am29LV008T/Am29LV008B
PRELIMINARY Embedded Program or Erase Algorithm is completed, DQ6 will stop toggling and valid data can be read on the next successive attempts. During programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four-write-pulse sequence. During Chip erase, the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six-write-pulse sequence. During Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during the Sector Erase time-out. Either CE or OE toggling will cause DQ6 to toggle. If the user attempts to write to a protected sector, DATA Polling will be activated for about 1 s; the device will then return to read mode, with data from the protected sector unchanged. If the user attempts to erase a protected sector, Toggle Bit will be activated for about 50 s; the device will then return to read mode, without having erased the protected sector. DQ5: Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions, DQ5 will produce a `1' indicating that the program or erase cycle was not successfully completed. Write operation status and reset command are the only operating functions under this condition. The device will draw active power under this condition. The DQ5 failure condition will also appear if the user attempts to write a data `1' to a bit that has already been programmed to a data `0'. In this case, the DQ5 failure condition is not guaranteed to happen, since the device was incorrectly used. Please note that programming a data `0' to a data `1' should never be attempted, and only erasure should be used for this purpose. If programming to a data `1' is attempted, the device should be reset. If the DQ5 failure condition is observed while in Sector Erase mode (that is, exceeded timing limits), then DQ2 can be used to determine which sector had the problem. This is especially useful when multiple sectors have been loaded for erase. DQ3: Sector Erase Timer After the completion of the initial Sector Erase command sequence, the Sector Erase time-out will begin. DQ3 will remain low until the time-out is complete. DATA Polling (DQ7) and Toggle Bit (DQ6) are also valid after the first sector erase command sequence. If DATA Polling or the Toggle Bit indicates the device has been written with a valid Sector Erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (`1'), the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by the DATA Polling or Toggle Bit. If DQ3 is low (`0'), the device will accept additional sector erase commands. To be certain the command has been accepted, the software should check the status of DQ3 following each Sector Erase command. If DQ3 was high on the second status check, the command may not have been accepted. It is recommended that the user guarantee the time between sector erase command writes be less than 80 s by disabling the processor interrupts just for the duration of the Sector Erase (30H) commands. This approach will ensure that sequential sector erase command writes will be written to the device while the sector erase timer window is still open. DQ2: Toggle Bit 2 This toggle bit, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspend-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase suspend-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic `1' at the DQ2 bit. Note that a sector which is selected for erase is not available for read in Erase Suspend mode. Other sectors which are not selected for Erase can be read in Erase Suspend. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or erase, or erase suspend-program operation is in progress. If the DQ5 failure condition is observed while in Sector Erase mode (that is, exceeded timing limits), the DQ2 toggle bit can give extra information. In this case, the normal function of DQ2 is modified. If DQ5 is at logic `1', then DQ2 will toggle with consecutive reads only at the sector address that caused the failure condition. DQ2 will toggle at the sector address where the failure occurred and will not toggle at other sector addresses.
3.0 V-only Flash
Am29LV008T/Am29LV008B
17
PRELIMINARY RY/BY: Ready/Busy Pin The Am29LV008 provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or have been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the Am29LV008 is placed in an Erase Suspend mode, the RY/BY output will be high. For programming, the RY/BY is valid (RY/BY=0) after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase, the RY/BY is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the RY/BY is also valid after the rising edge of the sixth WE pulse. Since the RY/BY pin is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
Table 7.
Mode Program Erase Erase-Suspend Read (Note 1) (Erase-Suspended Sector) Erase Suspend Program
Toggle Bit Status
DQ7 DQ7 0 1 DQ7 (Note 2) DQ6 Toggles Toggles 1 Toggles DQ2 1 Toggles Toggles 1 (Note 2)
Notes: 1. These status flags apply when outputs are read from a sector that has been erase suspended. 2. These status flags apply when outputs are read from the addresses of the non-erase suspended sector.
CE LAST_BUS_CYCLE WE
RY/BY tBUSY
20511C-4
Figure 1.
RY/BY Timing Diagram
18
Am29LV008T/Am29LV008B
PRELIMINARY RESET: Hardware Reset Pin The RESET pin is an active low signal. A logic `0' on this pin will force the device out of any mode that is currently executing back to the reset state. This allows a system reset to take effect immediately without having to wait for the device to finish a long execution cycle. To avoid a potential bus contention during a system reset, the device is isolated from the data I/O bus by tri-stating the data output pins for the duration of the RESET pulse. If RESET is asserted during a program or erase operation, the RY/BY pin will remain low until the reset operation is internally complete. This will require between 1 s and 20 s. Hence the RY/BY pin can be used to signal that the reset operation is complete. Otherwise, allow for the maximum reset time of 20 s. If RESET is asserted when a program or erase operation is not executing (RY/BY pin is high), the reset operation will be complete within 500 ns. Asserting RESET during a program or erase operation leaves erroneous data stored in the address locations being operated on at the time of device reset. These locations need updating after the reset operation is complete. See Figure 2 for timing specifications. The device enters ICC4 standby mode (200 nA) when VSS 0.3 V is applied to the RESET pin. The device can enter this mode at any time, regardless of the logical condition of the CE pin. Furthermore, entering ICC4 during a program or erase operation leaves erroneous data in the address locations being operated on at the time of the RESET pulse. These locations need updating after the device resumes standard operations. After the RESET pin goes high, a minimum latency period of 50 ns must occur before a valid read can take place.
3.0 V-only Flash
RESET
tRL
RY/BY tRRB
20511C-5
Figure 2.
Device Reset During a Program or Erase Operation
RESET
tRP
RY/BY 0V
20511C-6
Figure 3.
Device Reset During Read Mode
Am29LV008T/Am29LV008B
19
PRELIMINARY
Data Protection
The Am29LV008 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power-up, the device automatically resets the internal state machine to the read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of the command sequences. The Am29LV008 incorporates several features to prevent inadvertent write cycles resulting from V CC power-up and power-down transitions or system noise.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must be logical zero while OE is a logical one.
Power-Up Write Inhibit
Power up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power up.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (lock-out voltage). If VCC < VLKO, the command register is disabled and all internal program/ erase circuits are disabled. Under this condition, the device will reset to read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control levels are logically correct when VCC is above VLKO (unless the RESET pin is asserted).
20
Am29LV008T/Am29LV008B
PRELIMINARY
EMBEDDED ALGORITHMS Embedded Program Algorithm
3.0 V-only Flash
START
Write Program Cmd Sequence
Data Poll Device
Verify Byte?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
20511C-7
Figure 4.
Embedded Program Algorithm
Bus Operation Standby* Write Read Standby*
Command Sequence
Comments
Program
Valid Address/Data DATA Polling to Verify Programming Compare Data Output to Data Expected
* Device is either powered-down, erase inhibit, or program inhibit.
Am29LV008T/Am29LV008B
21
PRELIMINARY
Embedded Erase Algorithm
START
Write Erase Cmd Sequence
Data Poll from Device
No
Data = FFH?
Yes Erasure Completed
20511C-8
Figure 5.
Embedded Erase Algorithm
Bus Operation Standby Write Read Standby
Command Sequence
Comments
Erase DATA Polling to Verify Erasure Compare Output to FFH
22
Am29LV008T/Am29LV008B
PRELIMINARY
Data Polling Algorithm
3.0 V-only Flash
START
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Yes
DQ7 = Data?
No FAIL PASS
20511C-9
Figure 6.
Data Polling Algorithm
Am29LV008T/Am29LV008B
23
PRELIMINARY
Toggle Bit Algorithm
START
DQ6 = Toggle?
No
Yes No
DQ5 = 1?
Yes No
DQ6 = Toggle?
Yes FAIL PASS
20511C-10
Figure 7.
Toggle Bit Algorithm
Temporary Sector Unprotect Algorithm
Start
RESET = VID (Note 1) Perform Erase or Program Operations
RESET = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again.
20511C-11
Figure 8.
Temporary Sector Unprotect Algorithm
24
Am29LV008T/Am29LV008B
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to Ground All pins except A9, OE and RESET (Note 1) . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC+0.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . -0.5 V to +3.6 V A9, OE, and RESET (Note 2). . . . . . -0.5 V to +13.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Tables 10 and 11. 2. Minimum DC input voltage on pins A9, OE, and RESET is -0.5 V. During voltage transitions, A9, OE, and RESET may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. See Tables 10 and 11. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA). . . . . . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (TA). . . . . . . . . . -40C to +85C Extended (E) Devices Ambient Temperature (TA). . . . . . . . . -55C to +125C VCC Supply Voltages VCC for Am29LV008T/B-90R. . . . . . . . +3.0 V to 3.6 V VCC for Am29LV008T/B-100, -120, -150 . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
3.0 V-only Flash
Am29LV008T/Am29LV008B
25
PRELIMINARY
DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 ICC4 ICC5 VIL VIH VID VOL VOH1 VOH2 VLKO Low VCC Lock-Out Voltage (Note 4) Parameter Description Input Load Current A9 Input Load Current Output Leakage Current VCC Active Current (Note 1) VCC Active Current (Notes 1, 2, and 4) VCC Standby Current VCC Standby Current During Reset Automatic Sleep Mode (Note 3) Input Low Voltage Input High Voltage Voltage for Autoselect and Temporary VCC = 3.3 V Sector Unprotect Output Low Voltage Output High Voltage IOL = 4.0 mA, VCC = VCC min IOH = -2.0 mA, VCC = VCC min IOH = -100 A, VCC = VCC min 0.85 VCC VCC-0.4 2.3 2.5 V Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 13.0 V VOUT = VSS to VCC, VCC = VCC max CE = VIL, OE = VIH at 5 MHz CE = VIL, OE = VIH at 1 MHz CE = VIL, OE = VIH VCC = VCC max; CE, RESET = VCC 0.3 V VCC = VCC max; CE = VCC 0.3 V; RESET = VSS 0.3 V VIH = VCC 0.3 V; VIL = VSS 0.3 V -0.5 0.7 x VCC 11.5 Min Max 1.0 35 1.0 16 4 30 5 5 5 0.8 VCC + 0.3 12.5 0.45 Unit A A A mA mA mA A A A V V V V V
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Erase or Embedded Program is in progress. 3. Automatic sleep mode enables the low power mode when addresses remain stable for 200 ns. Typical sleep mode current is 200 nA. 4. Not 100% tested.
26
Am29LV008T/Am29LV008B
PRELIMINARY
DC CHARACTERISTICS (CONTINUED)
3.0 V-only Flash
25 Supply Current in mA
20
15
10
5 0 0 500 1000 1500 2000 Time in ns
Note: Addresses are switching at 1 MHz
20511C-11A
2500
3000
3500
4000
Figure 8A.
ICC Current vs. Time
15
Supply Current in mA
10
3.6 V
2.7 V
5
0 1
Note: T = 25 C
2
3 Frequency in MHz Figure 8B. ICC vs. Frequency
4
5
20511C-11B
Am29LV008T/Am29LV008B
27
PRELIMINARY
AC CHARACTERISTICS Read-Only Operations Characteristics
Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Standard tRC tACC tCE tOE tDF tDF tOH tReady Description Read Cycle Time (Note 3) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Notes 2, 3) Output Enable to Output High Z (Notes 2, 3) Output Hold Time From Addresses, CE or OE, Whichever Occurs First (Note 3) RESET Pin Low to Read Mode (Note 3) CE = VIL OE = VIL OE = VIL Test Setup Min Max Max Max Max Max Min Max Speed Option (Note 1) -90R 90 90 90 40 30 30 0 20 -100 100 100 100 40 30 30 0 20 -120 120 120 120 50 30 30 0 20 -150 150 150 150 55 40 40 0 20 Unit ns ns ns ns ns ns ns s
Notes: 1. Test Conditions Input Rise and Fall Times: 5 ns Input Pulse Levels: 0.0 V to 3.0 V Timing Measurement Reference Level: Input: 1.5 V Output: 1.5 V 2. Output Driver Disable Time 3. Not 100% tested.
3.3 V IN3064 or Equivalent
2.7 k
Device Under Test CL
6.2 k
IN3064 or Equivalent
IN3064 or Equivalent
Notes: CL = 30 pF for 90 and 100 ns CL = 100 pF for 120 and 150 ns
IN3064 or Equivalent
20511C-12
Figure 9.
Test Conditions
28
Am29LV008T/Am29LV008B
PRELIMINARY
AC CHARACTERISTICS Write (Erase/Program) Operations
3.0 V-only Flash
Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Standard Description tWC tAS tAH tDS tDH tOES tOEH Write Cycle Time (Note 2) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (Note 2) Output Enable Hold Time Read (Note 2) Toggle and Data Polling (Note 2) Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Min Min Min Min Min Min Min Max Min -90R 90 0 50 50 0 0 0 10 0 0 0 50 30 9 1 50 0 50 20 90 500 500 20 4 -100 100 0 50 50 0 0 0 10 0 0 0 50 30 9 1 50 0 50 20 90 500 500 20 4 -120 120 0 50 50 0 0 0 10 0 0 0 50 30 9 1 50 0 50 20 90 500 500 20 4 -150 150 0 65 65 0 0 0 10 0 0 0 65 35 9 1 50 0 50 20 90 500 500 20 4 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s sec s ns ns s ns ns ns s s
tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2
tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tRB tRH tRPD tBUSY tVIDR tRP t RRB tRSP
Read Recovery Time Before Write (OE High to WE Low) CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Programming Operation Sector Erase Operation (Note 1) VCC Setup Time Write Recovery Time from RY/BY RESET High Time Before Read RESET To Power Down Time Program/Erase Valid to RY/BY Delay Rise Time to VID RESET Pulse Width RESET Low to RY/BY High RESET Setup Time for Temporary Sector Unprotect
Notes: 1. The duration of the program or erase operation is variable and is calculated in the internal algorithms. 2. Note 100% tested.
Am29LV008T/Am29LV008B
29
PRELIMINARY
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns
20511C-13
Figure 10.
Maximum Negative Overshoot Waveform
20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns 20 ns
20511C-14
Figure 11.
Maximum Positive Overshoot Waveform
30
Am29LV008T/Am29LV008B
PRELIMINARY
SWITCHING WAVEFORMS
tRC Addresses CE tOE OE tOEH tCE HIGH Z Outputs Output Valid tDF Addresses Stable tACC
3.0 V-only Flash
WE
tOH HIGH Z
20511C-15
Figure 12.
AC Waveforms for Read Operations
tWC ADDRESSES 555H
tAS PA tAH
Data Polling PA tRC
CE tGHWL OE tWP WE tCS tWPH tDS tDH DATA
A0H PD DQ7 DOUT
tWHWH1_or_2 tDF tOE
tOH VCC tVCS tCE
Notes: 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA is the address of the memory location to be programmed. 4. PD is the data to be programmed at the byte address. 5. Illustration shows the last two cycles of a four-bus-cycle sequence..
20511C-16
Figure 13.
AC Waveforms for Program Operations
Am29LV008T/Am29LV008B
31
PRELIMINARY
SWITCHING WAVEFORMS
tWC ADDRESSES 555H tAS AAAH tAH CE tGHWL OE tWP WE tCS tDS tDH DATA
AAH 55H 80H AAH 55H 555H for chip erase
555H
555H
AAAH
SA
tWPH
10H for Chip Erase 30H
VCC
Note: 1. SA is the sector address for Sector Erase.
20511C-17
Figure 14.
AC Waveforms for Chip/Sector Erase Operations
tCH CE tOE OE tOEH tCE DQ7 tWHWH1_or_2 DQ0-DQ6
DQ0-DQ6=Invalid Data DQ0-DQ6 Valid Data DQ7
tDF
WE
*
tOH
DQ7=Valid Data
HIGH Z
HIGH Z
* DQ7 = Valid Data (The device has completed the embedded operation.)
20511C-18
Figure 15.
AC Waveforms for Data Polling During Embedded Algorithm Operations
32
Am29LV008T/Am29LV008B
PRELIMINARY
SWITCHING WAVEFORMS
CE
3.0 V-only Flash
tOEH WE tOES OE * Data (DQ0-DQ7) DQ6=Toggle DQ6=Toggle DQ6=Stop Toggling tOE DQ0-DQ7 Data Valid
DQ6 stops toggling (The device has completed the embedded operation.)
20511C-19
Figure 16.
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
CE The rising edge of the last WE signal WE Entire programming or erase operations
RY/BY tBUSY
DQ7 = Valid Data (The device has completed the embedded operation.)
20511C-20
Figure 17.
RY/BY Timing Diagram During Program/Erase Operations
RESET
tRP tReady
20511C-21
Figure 18.
RESET Timing Diagram
Am29LV008T/Am29LV008B
33
PRELIMINARY
SWITCHING WAVEFORMS
tVIDR
12 V
RESET
0 V or 3 V 0 V or 3 V
CE
WE tRSP
Program or Erase Command Sequence
20511C-22
Figure 19.
Temporary Sector Unprotect Timing Diagram
34
Am29LV008T/Am29LV008B
PRELIMINARY
AC CHARACTERISTICS Write (Erase/Program) Operations
Alternate CE Controlled Writes
Parameter Symbols JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Standard tWC tAS tAH tDS tDH tOES tOEH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Toggle and Data Polling Hold Time (Note 1) Read Recovery Time Before Write (OE High to WE Low) WE Setup Time WE Hold Time CE Pulse Width CE Pulse Width High Programming Operation Sector Erase Operation (Note 3) Read (Note 1) Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ -90R 90 0 50 50 0 0 0 10 0 0 0 50 30 9 1 -100 100 0 50 50 0 0 0 10 0 0 0 50 30 9 1 -120 120 0 50 50 0 0 0 10 0 0 0 50 30 9 1 -150 150 0 65 65 0 0 0 10 0 0 0 65 35 9 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s sec
3.0 V-only Flash
tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2
tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2
Notes: 1. Not 100% tested. 2. The duration of the program or erase operation is variable and is calculated in the internal algorithms. 3. Does not include the preprogramming time.
Am29LV008T/Am29LV008B
35
PRELIMINARY
SWITCHING WAVEFORMS
tWC ADDRESSES 555H tAS PA tAH WE tGHWL OE tCP CE tWS tCPH tDS tDH DATA
A0H PD DQ7 DOUT
Data Polling PA
tWHWH1_or_2
VCC tVCS
Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the complement of the data written to the device. 4. DOUT is the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
20511C-23
Figure 20.
Alternate CE Controlled Write Operation Timings
36
Am29LV008T/Am29LV008B
PRELIMINARY
ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Endurance Typ (Note 2) 1 19 9 9 1,000,000 300 27 Max (Note 3) 15 Unit s s s s cycles Comments
3.0 V-only Flash
Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Minimum 100,000 cycles guaranteed
Notes: 1. The typical program and erase times are considerably less than the maximum times since most bytes program or erase significantly faster than the worst case byte. The device enters the failure mode (DQ5="1") only after the maximum times given are exceeded. See the section on DQ5 for further information. 2. Except for erase and program endurance, the typical program and erase times assume the following conditions: 25 3.0 V C, VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. 3. Under worst case conditions of 90C, VCC = 2.7 V, 100,000 cycles. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5 for further information on command definitions.
LATCHUP CHARACTERISTICS
Min Input voltage with respect to VSS on all pins except I/O pins (including A9, OE, and RESET) Input voltage with respect to VSS on all I/O pins VCC Current -1.0 V -1.0 V -100 mA Max 13.0 V VCC + 1.0 V +100 mA
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE (Notes 1-2)
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
Am29LV008T/Am29LV008B
37
PRELIMINARY
DATA SHEET REVISION SUMMARY FOR AM29LV008
Distinctive Characteristics: Rearranged bullets. Renamed "2.7 to 3.6 volt, extended voltage range..." to "Single power supply operation." Under "Single power supply operation" and "High performance" bullets, defined standard and extended voltage ranges and added 90 ns speed option. Combined "Advanced power management" and "Low current consumption" bullets into new "Ultra low power consumption" bullet. Under that bullet, revised the typical standby and automatic sleep mode current specifications from 1 A to 200 nA; revised read current specification from 10 mA to 2 mA/MHz. Combined "Sector protection" and "Flexible sector architecture" bullets. Under flexible sector architecture bullet, added temporary sector unprotect feature description. Combined Embedded Program and Embedded Erase bullets under new "Embedded Algorithms" bullet; removed TM designations. Clarified descriptions of sector protection, erase suspend/resume, hardware reset pin, ready/busy pin, and data polling and toggle bits. General Description: Added text on new speed option and voltage range to the second paragraph. Product Selector Guide: Added -90R voltage range and speed option. Pin Configuration: Added new voltage range for -90R to VCC specification. Ordering Information, Standard Products: The -90R speed option is now listed in the example. Revised "Speed Option" section to indicate both voltage ranges.
sector protect verify. Added note 3 to explain sector protect codes. In Note 8, changed A13 to A11, added "unless otherwise noted"; is now new Note 6. RESET: Hardware Reset Pin: Fourth paragraph: Revised standby mode specification to 200 nA. Operating Ranges:
VCC Supply Voltages: Added 3.0 to 3.6 V voltage range and -90R speed option.
DC Characteristics:
CMOS Compatible: Changed ICC1 from 30 mA maximum at 6 MHz to 16 mA maximum at 5 MHz and 4 mA maximum at 1 MHz. Changed ICC2 from 35 mA to 30 mA maximum. In the VOL specification, changed the IOL test condition from 5.8 to 4.0 mA. In Note 1, changed 6 MHz to 5 MHz. In Note 3, changed address stable time from 300 ns to 200 ns; changed typical automatic sleep mode current from 1 A to 200 nA.
Figure 8A, ICC Current vs. Time, and Figure 8B, ICC vs. Frequency: Figure 8A illustrates current draw during the Automatic Sleep Mode after the addresses are stable. Figure 8B shows how frequency affects the current draw curves for both voltage ranges. AC Characteristics:
Read Only Operations Characteristics: Added -90R column.
Test Conditions, Figure 9: Added 90 ns speed to CL note. AC Characteristics:
Write/Erase/Program Operations: Added the -90R column.
Figure 13, AC Waveforms for Program Operations: Changed 5555H to 555H in addresses waveform to match command definitions (Table 5). Figure 14, AC Waveforms for Chip/Sector Erase Operations: Changed 5555H to 555H in addresses waveform to match command definitions (Table 5). Figure 19, Temporary Sector Unprotect Diagram: Corrected callouts on RESET waveform to "0 V or 3 V". AC Characteristics:
Valid Combinations: Added -90R speed option and voltage range.
Automatic Sleep Mode: Revised addresses stable time to 200 ns and current draw to 200 nA. Table 5, Command Definitions: Grouped address designators PA, PD, RA, RD, and SA under the legend heading. Modified SA definition to accommodate the sector protect verify command. Since unlock addresses only require address bits A0-A10 to be valid, the number of hexadecimal digits in the unlock addresses were changed from four to three. The remaining upper address bits are don't care. Removed "H" designation from hexadecimal values in table and replaced with new Note 1. Revised Notes 5 and 6 to indicate when commands are valid; are now new Notes 4 and 5. Expanded autoselect section to show each function separately: manufacturer ID, device ID, and
Alternate CE Controlled Writes: Added the -90R column. Changed tAH from 45 to 50 ns for -100, from 50 to 65 ns for -150. Changed tDS from 50 to 65 ns for -150. Changed tCP from 45 to 50 ns for -100, from 50 to 65 ns for -150. Changed tCPH from 20 to 30 ns for -100, 120; from 20 to 35 ns for -150.
38
Am29LV008T/Am29LV008B
PRELIMINARY Figure 20, Alternate CE Controlled Write Operation Timings: Changed 5555H to 555H in addresses waveform to match command definitions (Table 5). Erase and Programming Performance: Added typical chip erase specification. Renamed erase/program cycles specification to erase/program endurance. Corrected to indicate 1,000,000 cycle endurance is typical, not maximum, and that 100,000 cycle endurance is minimum, not typical. Revised Note 1 to include write endurance; moved Note 1 references in table to table head. Consolidated and moved Note 1 and Note 3 references in table to table head. Combined Note 2 and Note 5 into new Note 1, which applies to the entire table; revised to indicate that DQ5=1 after any maximum time. Comments for program and erase now straddle parameter rows. Separated the two sentences in Note 4 into new Notes 4 and 5; added corresponding note references to comment section.
3.0 V-only Flash
Am29LV008T/Am29LV008B
39

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